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"Bottom-up design of a high performance ultra-low power DFT utilizing ..."

Mohsen Jafari et al. (2013)

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DOI: 10.1109/DTIS.2013.6527804

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-22

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  - conf/dtis/JafariIFS13
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Mohsen Jafari, Mohsen Imani, Morteza Fathipour, Nader Sehatbakhsh:
Bottom-up design of a high performance ultra-low power DFT utilizing multiple-VDD, multiple-Vth and gate sizing. DTIS 2013: 178-179

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