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"An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC ..."

Radoslaw Czarnecki, Stanislaw Deniziak, Krzysztof Sapiecha (2003)

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DOI: 10.1109/DSD.2003.1231980

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  - https://dblp.org/rec/conf/dsd/CzarneckiDS03
Radoslaw Czarnecki, Stanislaw Deniziak, Krzysztof Sapiecha:
An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs. DSD 2003: 443-446

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