"Evaluation time Estimation for Pass Transistor Logic circuits."

P. W. Chandana Prasad et al. (2006)

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DOI: 10.1109/DELTA.2006.47

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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P. W. Chandana Prasad, Bruce Mills, Ali Assi, S. M. N. Arosha Senanayake, V. C. Prasad:
Evaluation time Estimation for Pass Transistor Logic circuits. DELTA 2006: 422-428

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