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"A Synthesisable VHDL Model for an Easily Testable Generalised Multiplier."

Syed Mahfuzul Aziz, C. N. Basheer, Joarder Kamruzzaman (2002)

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DOI: 10.1109/DELTA.2002.994685

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/delta/AzizBK02
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  persistent URL:
  - https://dblp.org/rec/conf/delta/AzizBK02
Syed Mahfuzul Aziz, C. N. Basheer, Joarder Kamruzzaman:
A Synthesisable VHDL Model for an Easily Testable Generalised Multiplier. DELTA 2002: 504-506

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