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"Logic synthesis method for pattern matching circuits implementation in ..."

Grzegorz Borowik, Tadeusz Luba, Bogdan J. Falkowski (2009)

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DOI: 10.1109/DDECS.2009.5012135

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - conf/ddecs/BorowikLF09
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  persistent URL:
  - https://dblp.org/rec/conf/ddecs/BorowikLF09
Grzegorz Borowik, Tadeusz Luba, Bogdan J. Falkowski:
Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories. DDECS 2009: 230-233

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