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"Power and Timing Modeling for ASIC Designs."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

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Wolfgang Roethig, A. M. Zarkesh, M. Andrews (1998)

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DOI: 10.1109/DATE.1998.655993

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Wolfgang Roethig, A. M. Zarkesh, M. Andrews:
Power and Timing Modeling for ASIC Designs. DATE 1998: 969-970

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last updated on 2023-03-24 00:02 CET by the dblp team

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