"A prototype VLSI chip architecture for JPEG image compression."

Mario Kovac, N. Ranganathan, Martin Zagar (1995)

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DOI: 10.1109/EDTC.1995.470428

access: closed

type: Conference or Workshop Paper

metadata version: 2022-05-20

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Mario Kovac, N. Ranganathan, Martin Zagar:
A prototype VLSI chip architecture for JPEG image compression. ED&TC 1995: 2-6

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