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"A parameterized timing-aware flip-flop merging algorithm for clock power ..."

Chaochao Feng et al. (2018)

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DOI: 10.23919/DATE.2018.8342131

access: closed

type: Conference or Workshop Paper

metadata version: 2018-04-24

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  - conf/date/FengYZL18
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Chaochao Feng, Daheng Yue, Zhenyu Zhao, Zhuofan Liao:
A parameterized timing-aware flip-flop merging algorithm for clock power reduction. DATE 2018: 881-884

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