"Hardware architecture for lowering the error floor of LTE turbo codes."

Thibaud Tonnellier et al. (2016)

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DOI: 10.1109/DASIP.2016.7853805

access: closed

type: Conference or Workshop Paper

metadata version: 2019-10-19

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Thibaud Tonnellier, Camille Leroux, Bertrand Le Gal, Christophe Jégo, Benjamin Gadat, Nicolas Van Wambeke:
Hardware architecture for lowering the error floor of LTE turbo codes. DASIP 2016: 107-112

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