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"Yield of VLSI circuits: myths vs. reality (panel)."

Andrzej J. Strojwas et al. (1986)

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DOI: 10.1145/318013.318050

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  dblp key:
  - conf/dac/StrojwasBBMS86
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  - https://dblp.org/rec/conf/dac/StrojwasBBMS86
Andrzej J. Strojwas, Clark Beck, Dennis Buss, Tülin Erdim Mangir, Charles H. Stapper:
Yield of VLSI circuits: myths vs. reality (panel). DAC 1986: 234-235

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