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"A formal method for computer design verification."

Vijay Pitchumani, Edward P. Stabler (1982)

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DOI: 10.1145/800263.809294

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  - conf/dac/PitchumaniS82
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  - https://dblp.org/rec/conf/dac/PitchumaniS82
Vijay Pitchumani, Edward P. Stabler:
A formal method for computer design verification. DAC 1982: 809-814

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