"FPGA Based Transient Fault Generate and Fault Tolerant for Asynchronous ..."

Y. N. Sharath Kumar, P. Dinesha (2020)

> Home

Details and statistics

DOI: 10.1007/978-3-030-51965-0_9

access: closed

type: Conference or Workshop Paper

metadata version: 2025-03-03

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/csoc/KumarD20
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/csoc/KumarD20
Y. N. Sharath Kumar, P. Dinesha:
FPGA Based Transient Fault Generate and Fault Tolerant for Asynchronous and Synchronous Circuits. CSOC (1) 2020: 103-110

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.