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"Lutsig: a verified Verilog compiler for verified circuit development."

Andreas Lööw (2021)

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DOI: 10.1145/3437992.3439916

access: closed

type: Conference or Workshop Paper

metadata version: 2021-02-12

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  dblp key:
  - conf/cpp/Loow21
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Andreas Lööw:
Lutsig: a verified Verilog compiler for verified circuit development. CPP 2021: 46-60

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