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"A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC ..."
Kesami Hagiwara et al. (2018)
- Kesami Hagiwara, Tomoichi Hayashi, Shumpei Kawasaki, Fumio Arakawa, Oleg Endo, Hayato Nomura, Akira Tsukamoto, Duong Nguyen, Binh Nguyen, Anh Tran, Hoan Hyunh, Ikuo Kudoh, Cong-Kha Pham
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A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications. COOL CHIPS 2018: 1-3
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