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"A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at ..."

Ming-Zhang Kuo et al. (2014)

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DOI: 10.1109/CICC.2014.6946030

access: closed

type: Conference or Workshop Paper

metadata version: 2021-01-13

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Ming-Zhang Kuo, Henry Hsieh, Sang H. Dhong, Ping-Lin Yang, Cheng-Chung Lin, Ryan Tseng, Kevin Huang, Min-Jer Wang, Wei Hwang:
A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. CICC 2014: 1-4

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