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"Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology."

Brian Campbell et al. (2007)

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DOI: 10.1109/CICC.2007.4405834

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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  - https://dblp.org/rec/conf/cicc/CampbellBJK07
Brian Campbell, James Burnette, Naveen Javarappa, Vincent von Kaenel:
Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology. CICC 2007: 729-732

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