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"A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent ..."

Darren Anand et al. (2007)

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DOI: 10.1109/CICC.2007.4405849

access: closed

type: Conference or Workshop Paper

metadata version: 2022-02-25

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Darren Anand, Jim Covino, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Mark Jacunski, Jake Paparelli, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva:
A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST. CICC 2007: 795-798

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