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"A 14.5 fJ/cycle/k-gate, 0.33 V ECG processor in 45nm CMOS using ..."

Rami A. Abdallah, Naresh R. Shanbhag (2012)

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DOI: 10.1109/CICC.2012.6330670

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Rami A. Abdallah, Naresh R. Shanbhag:
A 14.5 fJ/cycle/k-gate, 0.33 V ECG processor in 45nm CMOS using statistical error compensation. CICC 2012: 1-4

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