"A High Throughput/Gate AES Hardware Architecture by Compressing Encryption ..."

Rei Ueno et al. (2016)

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DOI: 10.1007/978-3-662-53140-2_26

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

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Rei Ueno, Sumio Morioka, Naofumi Homma, Takafumi Aoki:
A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation. CHES 2016: 538-558

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