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"Effect of MT and VT CMOS, on Transmission Gate Logic for Low Power 4: 1 ..."

Meenakshi Mishra, Shyam Akashe, Shyam Babu (2012)

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DOI: 10.1007/978-81-322-1041-2_12

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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Meenakshi Mishra, Shyam Akashe, Shyam Babu:
Effect of MT and VT CMOS, on Transmission Gate Logic for Low Power 4: 1 MUX in 45 nm Technology. BIC-TA (2) 2012: 139-150

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