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"At-Speed Built-in Test for Logic Circuits with Multiple Clocks."

Kazumi Hatayama, Michinobu Nakao, Yasuo Sato (2002)

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DOI: 10.1109/ATS.2002.1181726

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
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  - https://dblp.org/rec/conf/ats/HatayamaNS02
Kazumi Hatayama, Michinobu Nakao, Yasuo Sato:
At-Speed Built-in Test for Logic Circuits with Multiple Clocks. Asian Test Symposium 2002: 292-297

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