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"Synthesis of Sequential Circuits with Clock Control to Improve Testability."

Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth (1998)

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DOI: 10.1109/ATS.1998.741659

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/ats/EinspahrMS98
Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth:
Synthesis of Sequential Circuits with Clock Control to Improve Testability. Asian Test Symposium 1998: 472-

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