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"Modeling and Verifying Circuits Using Generalized Relative Timing."
Sanjit A. Seshia, Randal E. Bryant, Kenneth S. Stevens (2005)
- Sanjit A. Seshia, Randal E. Bryant, Kenneth S. Stevens:
Modeling and Verifying Circuits Using Generalized Relative Timing. ASYNC 2005: 98-108

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