"Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis."

Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein (2007)

> Home

Details and statistics

DOI: 10.1109/ASYNC.2007.10

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

- view
  authority control:
- export record
  dblp key:
  - conf/async/ChelceaVG07
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/async/ChelceaVG07
Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein:
Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis. ASYNC 2007: 117-128

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.