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"Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis."

Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein (2007)

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DOI: 10.1109/ASYNC.2007.10

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  dblp key:
  - conf/async/ChelceaVG07
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  persistent URL:
  - https://dblp.org/rec/conf/async/ChelceaVG07
Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein:
Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis. ASYNC 2007: 117-128

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