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"A 6.6pJ/bit/iter radix-16 modified log-MAP decoder using two-stage ACS ..."

Kai-Ting Shr et al. (2011)

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DOI: 10.1109/ASSCC.2011.6123575

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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Kai-Ting Shr, Yu-Cheng Chang, Chu-Yi Lin, Yuan-Hao Huang:
A 6.6pJ/bit/iter radix-16 modified log-MAP decoder using two-stage ACS architecture. A-SSCC 2011: 313-316

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