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"An on-chip timing jitter measurement circuit using a self-referenced clock ..."

Kiichi Niitsu et al. (2011)

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DOI: 10.1109/ASSCC.2011.6123637

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-21

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Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi:
An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation. A-SSCC 2011: 201-204

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