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"Fractional-N DPLL based low power clocking architecture for 1-14 Gb/s ..."

Masum Hossain et al. (2016)

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DOI: 10.1109/ASSCC.2016.7844142

access: closed

type: Conference or Workshop Paper

metadata version: 2021-07-25

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Masum Hossain, Amlan Nag, Waleed El-Halwagy, A. K. M. Delwar Hossain, Aurangozeb:
Fractional-N DPLL based low power clocking architecture for 1-14 Gb/s multi-standard transmitter. A-SSCC 2016: 89-92

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