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"A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized ..."

Hyun-A. Ahn et al. (2023)

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DOI: 10.1109/A-SSCC58667.2023.10348005

access: closed

type: Conference or Workshop Paper

metadata version: 2024-01-27

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  dblp key:
  - conf/asscc/AhnSKKKLGLJKCPLBMLBSYO23
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  persistent URL:
  - https://dblp.org/rec/conf/asscc/AhnSKKKLGLJKCPLBMLBSYO23
Hyun-A. Ahn, Yoo-Chang Sung, Yong-Hun Kim, Janghoo Kim, Kihan Kim, Donghun Lee, Young-Gil Go, Jae-Woo Lee, Jae-Woo Jung, Yong-Hyun Kim, Garam Choi, Jun-Seo Park, Bo-Hyeon Lee, Jin-Hyeok Baek, Daesik Moon, Daihyun Lim, Seung-Jun Bae, Young-Soo Sohn, Changsik Yoo, Tae-Young Oh:
A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications. A-SSCC 2023: 1-4

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