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"An enhanced iterative improvement method for evaluating the maximum number ..."

Kai Zhang et al. (1997)

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DOI: 10.1109/ASPDAC.1997.600068

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Kai Zhang, Haruhiko Takase, Terumine Hayashi, Hidehiko Kita:
An enhanced iterative improvement method for evaluating the maximum number of simultaneous switching gates for combinational circuits. ASP-DAC 1997: 107-112

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