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ORCID"Process-variation robust and low-power zero-skew buffered clock-tree ..."
Jeng-Liang Tsai, Charlie Chung-Ping Chen (2005)
- Jeng-Liang Tsai, Charlie Chung-Ping Chen:
Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling. ASP-DAC 2005: 1168-1171
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