"A ring-VCO-based sub-sampling PLL CMOS circuit with 0.73 ps jitter and ..."

Kenta Sogo, Akihiro Toya, Takamaro Kikkawa (2013)

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DOI: 10.1109/ASPDAC.2013.6509576

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Kenta Sogo, Akihiro Toya, Takamaro Kikkawa:
A ring-VCO-based sub-sampling PLL CMOS circuit with 0.73 ps jitter and 20.4 mW power consumption. ASP-DAC 2013: 101-102

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