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ORCID"A ring-VCO-based sub-sampling PLL CMOS circuit with 0.73 ps jitter and ..."
Kenta Sogo, Akihiro Toya, Takamaro Kikkawa (2013)
- Kenta Sogo, Akihiro Toya, Takamaro Kikkawa:
A ring-VCO-based sub-sampling PLL CMOS circuit with 0.73 ps jitter and 20.4 mW power consumption. ASP-DAC 2013: 101-102
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