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"An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST."
Liang-Che Li et al. (2015)
- Liang-Che Li, Wen-Hsuan Hsu, Kuen-Jong Lee, Chun-Lung Hsu:
An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. ASP-DAC 2015: 520-525
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