"An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST."

Liang-Che Li et al. (2015)

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DOI: 10.1109/ASPDAC.2015.7059059

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Liang-Che Li, Wen-Hsuan Hsu, Kuen-Jong Lee, Chun-Lung Hsu:
An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST. ASP-DAC 2015: 520-525

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