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"Efficient FPGA Routing Architecture Exploration Based on Two-Stage MUXes."

Jide Zhang et al. (2023)

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DOI: 10.1109/ASICON58565.2023.10395964

access: closed

type: Conference or Workshop Paper

metadata version: 2024-04-02

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  dblp key:
  - conf/asicon/ZhangZSWZ23
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  persistent URL:
  - https://dblp.org/rec/conf/asicon/ZhangZSWZ23
Jide Zhang, Kaixiang Zhu, Kaichuang Shi, Lingli Wang, Hao Zhou:
Efficient FPGA Routing Architecture Exploration Based on Two-Stage MUXes. ASICON 2023: 1-4

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