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"Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point ..."

Javier D. Bruguera, Tomás Lang (2005)

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DOI: 10.1109/ARITH.2005.22

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  dblp key:
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  - https://dblp.org/rec/conf/arith/BrugueraL05
Javier D. Bruguera, Tomás Lang:
Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition. IEEE Symposium on Computer Arithmetic 2005: 42-51

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