"Reduced Latency IEEE Floating-Point Standard Adder Architectures."

Andrew Beaumont-Smith et al. (1999)

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DOI: 10.1109/ARITH.1999.762826

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, Cheng-Chew Lim:
Reduced Latency IEEE Floating-Point Standard Adder Architectures. IEEE Symposium on Computer Arithmetic 1999: 35-

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