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"On design and performance of VLSI based parallel multiplier."

Dharma P. Agrawal et al. (1983)

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DOI: 10.1109/ARITH.1983.6158064

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Dharma P. Agrawal, Girish C. Pathak, Nikunja K. Swain, Bhuwan K. Agrawal:
On design and performance of VLSI based parallel multiplier. IEEE Symposium on Computer Arithmetic 1983: 17-21

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