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"40-nm 2×VDD Digital Output Buffer Design With DDR4-Compliant Slew Rate."
Chua-Chin Wang, Zong-You Hou, Ssu-Wei Huang (2018)
- Chua-Chin Wang, Zong-You Hou, Ssu-Wei Huang:
40-nm 2×VDD Digital Output Buffer Design With DDR4-Compliant Slew Rate. APCCAS 2018: 279-282
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