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"Efficient Hardware Design of Parameterized Posit Multiplier and Posit Adder."

Sadhu Sai Ram, Kuruvilla Varghese (2023)

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DOI: 10.1109/APCCAS60141.2023.00083

access: closed

type: Conference or Workshop Paper

metadata version: 2024-05-10

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Sadhu Sai Ram, Kuruvilla Varghese:
Efficient Hardware Design of Parameterized Posit Multiplier and Posit Adder. APCCAS 2023: 343-347

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