"Timing analysis and optimization of voltage scaled CMOS digital circuits ..."

Anne Lorraine S. Luna, John Richard E. Hizon, Louis P. Alarcón (2014)

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DOI: 10.1109/APCCAS.2014.7032782

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Anne Lorraine S. Luna, John Richard E. Hizon, Louis P. Alarcón:
Timing analysis and optimization of voltage scaled CMOS digital circuits with dual-Vth devices. APCCAS 2014: 312-315

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