BibTeX record conf/apccas/ChenGSA16

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@inproceedings{DBLP:conf/apccas/ChenGSA16,
  author    = {Wei{-}Yang Chen and
               Daniel G{\"{u}}nther and
               Chung{-}An Shen and
               Gerd Ascheid},
  title     = {Design and implementation of a low-latency, high-throughput sorted
               {QR} decomposition circuit for {MIMO} communications},
  booktitle = {2016 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS}
               2016, Jeju, South Korea, October 25-28, 2016},
  pages     = {277--280},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/APCCAS.2016.7803953},
  doi       = {10.1109/APCCAS.2016.7803953},
  timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
  biburl    = {https://dblp.org/rec/conf/apccas/ChenGSA16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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