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"The logical design of a 1-microsecond parallel adder using 1-megacycle ..."

Arnold Weinberger, Jay L. Smith (1956)

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DOI: 10.1145/1455410.1455450

access: closed

type: Conference or Workshop Paper

metadata version: 2021-04-22

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  - conf/aieeire/WeinbergerS56
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  - https://dblp.org/rec/conf/aieeire/WeinbergerS56
Arnold Weinberger, Jay L. Smith:
The logical design of a 1-microsecond parallel adder using 1-megacycle circuitry. AIEE-IRE Computer Conference (Western) 1956: 103-108

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