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"TAC-RAM: A 65nm 4Kb SRAM Computing-in-Memory Design with 57.55 TOPS/W ..."

Xiaomeng Wang et al. (2022)

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DOI: 10.1109/AICAS54282.2022.9869970

access: closed

type: Conference or Workshop Paper

metadata version: 2024-02-05

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  dblp key:
  - conf/aicas/WangLHZCLKTT22
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Xiaomeng Wang, Xuejiao Liu, Xianghong Hu, Xiaopeng Zhong, Xizi Chen, Yu Liu, Patrick Kong, Fengshi Tian, Chi-Ying Tsui:
TAC-RAM: A 65nm 4Kb SRAM Computing-in-Memory Design with 57.55 TOPS/W supporting Multibit Matrix-Vector Multiplication for Binarized Neural Network. AICAS 2022: 66-69

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