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"FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient ..."

Ayan Palchaudhuri, Anindya Sundar Dhar (2019)

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DOI: 10.1109/IEEECONF44664.2019.9049071

access: closed

type: Conference or Workshop Paper

metadata version: 2022-04-09

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Ayan Palchaudhuri, Anindya Sundar Dhar:
FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation. ACSSC 2019: 1555-1559

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