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"High performance two-stage charge-pump for spur reduction in CMOS PLL."

Jung-Woong Park et al. (2014)

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DOI: 10.1109/SSD.2014.6808749

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  dblp key:
  - conf/IEEEssd/ParkKJWC14
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  - https://dblp.org/rec/conf/IEEEssd/ParkKJWC14
Jung-Woong Park, Nam-Soo Kim, Hye-Im Jeong, Da-Sol Won, Ho-Yong Choi:
High performance two-stage charge-pump for spur reduction in CMOS PLL. SSD 2014: 1-7

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