BibTeX record journals/tvlsi/YinYLLW16

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@article{DBLP:journals/tvlsi/YinYLLW16,
  author       = {Shouyi Yin and
                  Xianqing Yao and
                  Dajiang Liu and
                  Leibo Liu and
                  Shaojun Wei},
  title        = {Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {24},
  number       = {5},
  pages        = {1895--1908},
  year         = {2016},
  url          = {https://doi.org/10.1109/TVLSI.2015.2474129},
  doi          = {10.1109/TVLSI.2015.2474129},
  timestamp    = {Fri, 27 Mar 2020 08:39:50 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/YinYLLW16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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