BibTeX record journals/tvlsi/WangLYZCYW14

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@article{DBLP:journals/tvlsi/WangLYZCYW14,
  author       = {Yansheng Wang and
                  Leibo Liu and
                  Shouyi Yin and
                  Min Zhu and
                  Peng Cao and
                  Jun Yang and
                  Shaojun Wei},
  title        = {On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture
                  to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference
                  Time},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {22},
  number       = {5},
  pages        = {983--994},
  year         = {2014},
  url          = {https://doi.org/10.1109/TVLSI.2013.2263155},
  doi          = {10.1109/TVLSI.2013.2263155},
  timestamp    = {Fri, 27 Mar 2020 08:39:50 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/WangLYZCYW14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}