BibTeX record journals/tvlsi/ChenLY16

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@article{DBLP:journals/tvlsi/ChenLY16,
  author       = {Pai{-}Yu Chen and
                  Zhiwei Li and
                  Shimeng Yu},
  title        = {Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {24},
  number       = {12},
  pages        = {3460--3467},
  year         = {2016},
  url          = {https://doi.org/10.1109/TVLSI.2016.2553123},
  doi          = {10.1109/TVLSI.2016.2553123},
  timestamp    = {Thu, 16 Nov 2023 09:03:05 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ChenLY16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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