BibTeX record journals/jssc/LeeCSKKKKJKPKKCRCKKCC12

• > Home > journals/jssc/LeeCSKKKKJKPKKCRCKKCC12

@article{DBLP:journals/jssc/LeeCSKKKKJKPKKCRCKKCC12,
  author       = {Hyun{-}Woo Lee and
                  Hoon Choi and
                  Beom{-}Ju Shin and
                  Kyung{-}Hoon Kim and
                  Kyung Whan Kim and
                  Jaeil Kim and
                  Kwang Hyun Kim and
                  Jongho Jung and
                  Jae{-}Hwan Kim and
                  Eun Young Park and
                  Jong{-}Sam Kim and
                  Jong{-}Hwan Kim and
                  Jin{-}Hee Cho and
                  Nam Gyu Rye and
                  Jun Hyun Chun and
                  Yunsaing Kim and
                  Chulwoo Kim and
                  Young{-}Jung Choi and
                  Byong{-}Tae Chung},
  title        = {A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered {CAS}
                  Latency Controller for {DRAM} Interfaces},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {47},
  number       = {6},
  pages        = {1436--1447},
  year         = {2012},
  url          = {https://doi.org/10.1109/JSSC.2012.2191027},
  doi          = {10.1109/JSSC.2012.2191027},
  timestamp    = {Sun, 30 Aug 2020 00:13:07 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/LeeCSKKKKJKPKKCRCKKCC12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}