BibTeX record journals/jsa/VeglisPP00

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@article{DBLP:journals/jsa/VeglisPP00,
  author       = {Andreas A. Veglis and
                  Andreas S. Pombortsis and
                  Efstathios Papaefstathiou},
  title        = {Performance evaluation of a bus-based multistage multiprocessor architecture},
  journal      = {J. Syst. Archit.},
  volume       = {46},
  number       = {1},
  pages        = {39--47},
  year         = {2000},
  url          = {https://doi.org/10.1016/S1383-7621(98)00061-7},
  doi          = {10.1016/S1383-7621(98)00061-7},
  timestamp    = {Mon, 15 Jun 2020 16:50:42 +0200},
  biburl       = {https://dblp.org/rec/journals/jsa/VeglisPP00.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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