BibTeX record journals/jsa/KrishnaswamyGB97

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@article{DBLP:journals/jsa/KrishnaswamyGB97,
  author       = {Venkatram Krishnaswamy and
                  Rajesh Gupta and
                  Prithviraj Banerjee},
  title        = {Implications of {VHDL} timing models on simulation and software synthesis},
  journal      = {J. Syst. Archit.},
  volume       = {44},
  number       = {1},
  pages        = {23--36},
  year         = {1997},
  url          = {https://doi.org/10.1016/1383-7621(97)80001-X},
  doi          = {10.1016/1383-7621(97)80001-X},
  timestamp    = {Tue, 19 May 2020 15:54:57 +0200},
  biburl       = {https://dblp.org/rec/journals/jsa/KrishnaswamyGB97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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